Image sensors find applications in a wide variety of fields, including machine vision, robotics, guidance and navigation, automotive applications, and consumer products. In many smart image sensors, it is desirable to integrate on-chip circuitry to control the image sensor and to perform signal and image processing on the output image. Unfortunately, charge-coupled devices (CCD), which have been one of the dominant technologies used for image sensors, do not easily lend themselves to large scale signal processing and are not easily integrated with CMOS circuits. Moreover, a CCD is read out by sequentially transferring the signal charge through the semiconductor, and the readout rate is limited by the need for nearly perfect charge transfer.
Active pixel sensors (APS), which have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies and promise higher readout rates compared to passive pixel sensors. Active pixel sensors are often arranged as arrays of elements, which can be read out, for example, a column at a time. Each column can be read out at one time, driven and buffered for sensing by a readout circuit.
FIG. 1 shows an exemplary CMOS active pixel sensor integrated circuit chip that includes an array of active pixel sensors 30 and a controller 32 that provides timing and control signals to enable the reading out of signals stored in the pixels. Exemplary arrays have dimensions of N by M pixels and, in general, the size of the array 30 will depend on the particular implementation. The imager is read out a row at a time using a column parallel readout architecture. The controller 32 selects a particular row of pixels in the array 30 by controlling the operation of vertical addressing circuit 34 and row drivers 40. Charge signals stored in the selected row of pixels are provided to a readout circuit 42. The pixels of the columns can be read out sequentially using a horizontal addressing circuit 44. Typically, each pixel provides a reset output signal Vout1 and a signal representing accumulated charge during an integration period Vout2 which are provided at the output of the readout circuit 42.
As shown in FIG. 2, the array 30 includes multiple columns 49 of CMOS active pixel sensors 50. Each column 49 includes multiple rows of sensors 50. Signals from the active pixel sensors 50 in a particular column can be read out to a readout circuit 52 associated with that column. Signals stored in the readout circuits 52 can be sent to an output stage 54, which is common to the entire array of pixels 30. The analog output signals can then be sent, for example, to a differential analog-to-digital converter (ADC).
Excessive noise and slow frame rates are introduced during the read process of the differential charge mode readout from the columns of the CMOS image sensor. To compensate for this, current readout circuitry uses subsampling (under a sub-resolution mode) to increase the frame rate. In most imaging applications, a pixel is captured with each pulse of the pixel clock (except during blanking). Subsampling increases frame rates by capturing pixels at a rate slower than the base pixel clock frequency. For example, one pixel can be captured for every two pulses of the pixel clock to provide an effective sampling rate that is ½ the base pixel clock frequency. The use of subsampling allows a higher frequency pixel clock rate to clock lower-frequency sampling.
During subsampling, however, pixels are read out sequentially, but not contiguously. In other words, some pixels are skipped to obtain a lower resolution in exchange for a potentially higher frame rate. What is needed is an image sensor where the readout circuitry has improved sub-resolution characteristics with reduced aliasing.